In the case of flow simulations (CFD) the computational problem can be defined on a 2D or 3D array (NxM, NxMxL) type Virtual Cellular Machine while the operation of each processing element is described as a mathematical expression, acyclic data flow graph or UMF diagram. The problem to be solved is how to map the computational problem on a virtual array to a given physical FPGA where area/processor (logic slices, DSP slices), on-chip memory (BRAM) and off-chip memory bandwidth are limited. To conserve memory bandwidth the arrays are computed serially as a 1D stream of cells.